IP/Subsystem Verification Lead

PMTS SILICON DESIGN ENGINEER THE ROLE: AMD is looking for a talented individual to join the Network Technology Solutions Group in the Data Center Solutions Group as Principal Design Verification Engineer. This group designs and develops RTL blocks, subsystems, and SOCs for the AMD NTSG BU with product lines including AI NICs, low latency, High speed NIC, Networking of GPU clusters to be built to support AI training and inference workloads at scale. THE PERSON: As a Principal Design Verification Engineer, you will lead the verification efforts to functionally verify complex RTL blocks and SOCs destined for the next generation of Data Center networking ASICs KEY RESPONSIBILITIES: Experience of working as a technical lead in a verification team Proven track record in simulation-based verification for ASIC or FPGA blocks and subsystems. Strong experience in UVM-based verification in SystemVerilog, with a deep understanding of the framework. Experience of verification coverage closure in an ASIC or FPGA project. Strong problem-solving skills. Experience of Synopsys functional verification tools would be an advantage. Experience of full chip verification would be an advantage. Experience of formal verification would be an advantage. Knowledge of AI-based debug techniques would be an advantage. Knowledge of Python would be an advantage. Experience in C/C++ would be an advantage. RTL design experience would be an advantage. Experience in networking technologies and products would be an advantage. PREFERRED EXPERIENCE: Minimum 15 Year of experience in verification of VLSI systems ACADEMIC CREDENTIALS: Bachelor s or Master s degree in related discipline preferred Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.