IR/EM Engineer

KEY RESPONSIBILITIES: Lead IR/EM (Static IR, Dynamic IR, Power EM and Signal EM) analysis and signoff activities for complex SoC/IP designs from floorplan stage through tapeout. Own power integrity closure by driving IR-drop, electromigration, rush current, power-grid and power-delivery-network (PDN) optimization across multiple design stages. Collaborate with Physical Design, STA, Power Architecture, Package, Library and Full-Chip teams to achieve robust power integrity signoff. Perform early power-grid analysis, bump planning validation, power-domain verification, and design reviews to ensure signoff readiness. Analyze EMIR violations, determine root causes, define corrective actions, and drive ECO implementation and verification. Develop methodologies, automation, and flows for power integrity analysis, debug, reporting, and closure. Work closely with CAD teams and EDA vendors to improve EMIR signoff efficiency, accuracy, runtime, and scalability. Provide technical leadership and mentoring for engineers on power integrity concepts, EMIR closure methodologies, and best practices. Drive project planning, execution, risk assessment, and convergence tracking for IR/EM signoff milestones. Support Full-Chip signoff including power delivery analysis, TSV/uBump coverage validation, package interactions, and tapeout readiness reviews. PREFERRED EXPERIENCE: Experienced Physical Design / Power Integrity professional with a minimum of 10-12 years of industry experience in EMIR, Physical Design, STA, and signoff methodologies. Strong expertise in Static IR, Dynamic IR, Power EM, Signal EM, ESD, power-grid analysis, PDN design, and power integrity closure. Hands-on experience with industry-standard EMIR tools such as RedHawk, Voltus, PrimeRail, Totem, Celsius, or equivalent platforms. Good understanding of Physical Design flow including Floorplanning, Placement, CTS, Routing, Timing Closure, Physical Verification, and Tapeout. Experience with advanced technology nodes (5nm/4nm/3nm and beyond) and low-voltage/high-performance designs. Strong understanding of Power, Performance, Area (PPA) trade-offs and their impact on power integrity. Experience in automation using Perl, TCL, Shell, Python and Linux/Unix environments. Excellent problem-solving, technical leadership, presentation and communication skills. Experience driving cross-functional technical reviews and leading power integrity closure for multiple successful tapeouts. Qualifications: B.Tech/M.Tech/MS/Ph.D. in Electronics, Electrical Engineering, Computer Engineering, or a related discipline. Minimum 10+ years of relevant experience in Power Integrity, EMIR Signoff, Physical Design, or SoC Implementation. Proven track record of leading EMIR closure and signoff for multiple successful silicon tapeouts. Proficient in EMIR, Physical Design and signoff EDA tools including RedHawk, Voltus, PrimeRail, ICC2/Fusion Compiler, Innovus, PrimeTime and Calibre. Strong understanding of advanced-node design challenges, power delivery networks, package interaction, and full-chip signoff methodologies. Ability to lead technical discussions, mentor engineers, and drive project execution independently. Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.