Design Technology and Engineering

As an RTL Design Engineer (ASIC) at our company, you will be responsible for designing and implementing RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Your key responsibilities will include: - Developing micro-architecture specifications and delivering high-quality, synthesizable RTL. - Integrating complex subsystems into SoC environments and supporting design convergence. - Collaborating with system architects, verification, SoC, software, DFT, and physical design teams. - Applying low-power design techniques such as clock gating, power gating, and multi-voltage domains. - Analyzing and optimizing for performance, area, and power. - Ensuring protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. Qualifications required for this role include: - 13 years of experience in digital front-end ASIC/RTL design. - Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. - Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. - Experience with wireless modem IPs or similar high-performance digital blocks is a plus. - Familiarity with low-power design methodologies and CDC handling. - Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. - Self-motivated with a collaborative mindset and ability to work with minimal supervision. About the company: ACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. As an RTL Design Engineer (ASIC) at our company, you will be responsible for designing and implementing RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Your key responsibilities will include: - Developing micro-architecture specifications and delivering high-quality, synthesizable RTL. - Integrating complex subsystems into SoC environments and supporting design convergence. - Collaborating with system architects, verification, SoC, software, DFT, and physical design teams. - Applying low-power design techniques such as clock gating, power gating, and multi-voltage domains. - Analyzing and optimizing for performance, area, and power. - Ensuring protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. Qualifications required for this role include: - 13 years of experience in digital front-end ASIC/RTL design. - Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. - Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. - Experience with wireless modem IPs or similar high-performance digital blocks is a plus. - Familiarity with low-power design methodologies and CDC handling. - Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. - Self-motivated with a collaborative mindset and ability to work with minimal supervision. About the company: ACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes.