Padmi

Senior DFT Engineer

BangalorePosted 4 months ago
Electrical Electronics And Computer Hardware EngineeringSeniorFull Time
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Senior DFT Engineer Job Description PDL: Writing ICL and PDL by Own Debug protocols: Strong understanding on Jtag 1149.1-2013, ijtag - P1687 Debug patterns exposure: .V, optional STIL or SVF SSN + SSH architecture understanding. Tessent tool exposure: TestKompress, Tessent shell Scripting: TCL, shell Optional Skills (Good to have) SCAN architecture, past TAP/JTAG related DV feature. Patterns re-targetting Good Debug skills on the same. Experience: 4 to 5 Years Location: Bangalore

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Senior DFT Engineer at ALTEN Calsoft Labs · Padmi