Senior Physical Design Engineer

Physical Verification Engineer Company: ACL Digital Location: Pune Experience: 6 – 10 Years Domain: Semiconductor / VLSI / ASIC Role Overview: We are looking for an experienced Physical Verification Engineer to join our VLSI team. The candidate will be responsible for full-chip and block-level physical verification , ensuring layout correctness and manufacturability before tape-out. The role requires strong expertise in DRC, LVS, ERC, and sign-off flows along with collaboration across Physical Design, Layout, and CAD teams. Key Responsibilities: Perform Physical Verification sign-off checks including: DRC (Design Rule Check) LVS (Layout vs Schematic) ERC (Electrical Rule Check) Antenna checks Density / DFM checks Debug and resolve DRC/LVS violations with layout and design teams. Handle block-level and full-chip physical verification . Work with foundry rule decks and ensure compliance. Perform parasitic extraction (PEX) and support timing/SI teams. Support tape-out activities and sign-off closure . Develop automation scripts for verification flows. Mentor junior engineers and support project planning. Required Skills: Strong experience in Physical Verification tools : Calibre (DRC, LVS, PEX) IC Validator (ICV) or Cadence PVS Good understanding of: ASIC Physical Design flow CMOS layout concepts GDSII / OASIS formats Experience in advanced technology nodes (16nm / 7nm / 5nm preferred).