Place and Route Design Automation Engineer

As a Place & Route (P&R) Design Automation Engineer at Altera, you will play a crucial role in developing and supporting automated P&R tools, flows, and methodologies for next-generation FPGA silicon design. Your collaboration with physical design, CAD, and cross-functional engineering teams will focus on improving quality of results, runtime efficiency, and overall flow robustness. This position is ideal for individuals with hands-on P&R or physical design experience who are eager to enhance their expertise in semiconductor design automation. Key Responsibilities: - Work on Place & Route tools, flows, and methodologies for FPGA silicon design development. - Contribute to the development of new methodologies for next-generation Place & Route flows and tool enhancements. - Help maintain and improve existing P&R automation flows and infrastructure. - Provide end-user support for flow tools, including debugging issues and promoting best practices. - Develop and enhance scripts and automation utilities to improve usability, efficiency, and scalability. - Support improvements in P&R quality of results (timing, power, congestion, density, and overall design closure). - Assist in evaluating and testing new P&R tool capabilities and methodologies. - Identify design or flow bottlenecks and implement practical optimizations. - Collaborate closely with multi-geo teams across physical design, RTL, synthesis, and CAD to ensure robust end-to-end flow support. - Document methodologies, flow updates, and usage guidelines. Qualifications: - Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, with 3+ years of industry experience in semiconductor design or design automation. - 3+ years of hands-on experience in Place & Route (P&R), physical design, or design automation within FPGA or ASIC development environments. - 3+ years of experience working with Place & Route tools and strong applied knowledge of P&R algorithms, methodologies, and design flows. - 3+ years of experience using industry-standard EDA vendor tools (e.g., Synopsys and Cadence P&R tool suites) in production design environments. - 3+ years of strong coding experience in Tcl, Perl, and Python for automation, scripting, and tool integration. - 3+ years of experience working in Unix/Linux development environments. - 3+ years of experience applying physical design fundamentals, including floorplanning, placement, clocking, routing, and static timing analysis (STA). - 3+ years of experience debugging and resolving tool, flow, or design issues in a collaborative engineering environment. - 3+ years of experience collaborating with cross-functional and/or multi-geo engineering teams to support design execution. If you are passionate about driving innovation in FPGA silicon design through automated P&R tools and methodologies, Altera offers an exciting opportunity to contribute to cutting-edge technology solutions. Join us in our mission to deliver the worlds most advanced and efficient programmable technology. As a Place & Route (P&R) Design Automation Engineer at Altera, you will play a crucial role in developing and supporting automated P&R tools, flows, and methodologies for next-generation FPGA silicon design. Your collaboration with physical design, CAD, and cross-functional engineering teams will focus on improving quality of results, runtime efficiency, and overall flow robustness. This position is ideal for individuals with hands-on P&R or physical design experience who are eager to enhance their expertise in semiconductor design automation. Key Responsibilities: - Work on Place & Route tools, flows, and methodologies for FPGA silicon design development. - Contribute to the development of new methodologies for next-generation Place & Route flows and tool enhancements. - Help maintain and improve existing P&R automation flows and infrastructure. - Provide end-user support for flow tools, including debugging issues and promoting best practices. - Develop and enhance scripts and automation utilities to improve usability, efficiency, and scalability. - Support improvements in P&R quality of results (timing, power, congestion, density, and overall design closure). - Assist in evaluating and testing new P&R tool capabilities and methodologies. - Identify design or flow bottlenecks and implement practical optimizations. - Collaborate closely with multi-geo teams across physical design, RTL, synthesis, and CAD to ensure robust end-to-end flow support. - Document methodologies, flow updates, and usage guidelines. Qualifications: - Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, with 3+ years of industry experience in semiconductor design or design automation. - 3+ years of hands-on experience in Place & Route (P&R), physical design, or design automation within FPGA or ASIC development environments. - 3+ years of experien