Senior Design Verification Engineer

Position: Senior Design Verification Engineer (SoC / PCIe / CXL) Location: Pune / Bangalore / Hyderabad / Ahmedabad Experience: 7+ Years Employment Type: Full-time About The Opportunity Best NanoTech is looking for a seasoned Senior Design Verification Engineer. We are looking for a hands-on technical leader to manage SoC verification efforts for next-generation chips involving high-speed protocols like CXL, HBM, and PCIe. Key Responsibilities Lead Verification Efforts: Manage and execute end-to-end SoC Design Verification plans for complex projects, ensuring zero-bug silicon. Strategy & Architecture: Develop comprehensive verification strategies, test plans, and robust test benches. Protocol Verification: Verify high-speed interfaces (PCIe, Ethernet, CXL, MIPI, DDR, HBM) and standard peripherals (I2C/I3C, SPI, UART, GPIO, QSPI). Coverage Closure: Analyze and implement SystemVerilog Assertions (SVA) and drive coverage closure (Code, Toggle, Functional). Timeline Management: Demonstrate strong ownership of project goals, ensuring critical deadlines are met with high quality. Required Skills & Qualifications Experience: 7+ years of relevant industry experience in VLSI/ASIC Verification. Core Skills: Strong command over SystemVerilog and UVM methodology. Protocol Knowledge: Deep understanding of high-speed protocols (PCIe, CXL, DDR/HBM) is mandatory. Debugging: Proficiency in debugging complex SoC scenarios. Preferred Skills (Added Advantage) Experience with Gate-Level Simulations (GLS). Power-Aware Verification expertise using UPF and Xprop. Why Join Us Work on the bleeding edge of technology (CXL, HBM, 3nm nodes). Flexible location options across major tech hubs (Pune, BLR, Hyd, Ahd). Collaborative culture with direct mentorship from industry veterans. How To Apply If you are ready to take ownership of complex SoC projects, apply via LinkedIn or send your resume directly to [HIDDEN TEXT] . #DesignVerification #SoC #PCIe #CXL #HBM #VLSIJobs #Semiconductor #BestNanoTech #Hiring