SOC Design Manager

Title-System on Chip -Design Manager Experience- 12-17 Years Location: Hyderabad Type: Full-Time, On-Site Notice Period - Immediate Joiner / serving notice period About the Role As Senior SoC Design Manager, you will lead the design and development of Azimuth AI's next-generation mixed-signal, ARM-based SoCs. You will build and guide a world-class engineering team in Hyderabad and play a critical role in shaping our silicon roadmap for embedded AI compute. You'll work at the intersection of hardware, software, and AI, driving end-to-end SoC execution — from concept and architecture through tape-out and production. This is a high-impact, senior leadership role for someone who thrives on both technical excellence and organizational leadership. Responsibilities Lead the design, development, and delivery of mixed-signal SoCs integrating ARM cores, analog interfaces, and custom AI acceleration IP. Manage and mentor a talented team of design engineers, fostering innovation, ownership, and collaboration. Work cross-functionally with system architects, firmware, and software teams to achieve true hardware–software co-design for software-defined flexibility. Drive SoC design flow optimization across RTL, verification, physical implementation, and silicon validation. Partner with EDA vendors, foundries, and IP suppliers to deliver first-pass silicon success on advanced technology nodes. Contribute to Azimuth AI's long-term silicon and embedded AI compute roadmap. Shape design methodologies, quality standards, and technical culture within the hardware engineering organization. Qualifications Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related discipline. 12+ years of SoC/ASIC design experience with at least 5 years of leadership or management roles. Required Skills Proven track record of mixed-signal SoC tape-outs — ideally in embedded, automotive, or AI-driven applications. Deep understanding of ARM-based architectures, RTL design, IP integration, and analog/digital co-design. Strong knowledge of verification, timing closure, and silicon bring-up methodologies. Experience integrating AI accelerators, NNEs, or domain-specific compute IPs. Excellent leadership, communication, and collaboration skills across global, cross functional teams.