Principal Design Engineers

As a Design Verification Engineer at Cadence, you will play a crucial role in verifying complex designs and leading projects from concept to verification closure. You will have the opportunity to work on cutting-edge technologies in the world of VLSI and contribute to the development of innovative solutions. Key Responsibilities: - Utilize your 8+ years of Design Verification experience with SV/UVM to ensure the functional correctness of designs. - Demonstrate a strong background in functional verification fundamentals, environment planning, and test plan generation. - Lead the development of functional verification environments using UVM and System Verilog coding. - Verify memory IP such as DDR, HBM, and GDDR, adding value through your prior experience in IP verification. Qualifications Required: - BE/BTech/ME/MTech in Electrical/Electronics/VLSI with a focus on design and verification engineering. - Proficiency in UVM and System Verilog coding for functional verification environment development. - Experience in IP verification of memory IP would be an added advantage. Cadence is a company where meaningful work is done, and where your contributions can make a real impact. Join us in solving challenges that others cannot tackle, and be a part of a team that is shaping the future of technology. As a Design Verification Engineer at Cadence, you will play a crucial role in verifying complex designs and leading projects from concept to verification closure. You will have the opportunity to work on cutting-edge technologies in the world of VLSI and contribute to the development of innovative solutions. Key Responsibilities: - Utilize your 8+ years of Design Verification experience with SV/UVM to ensure the functional correctness of designs. - Demonstrate a strong background in functional verification fundamentals, environment planning, and test plan generation. - Lead the development of functional verification environments using UVM and System Verilog coding. - Verify memory IP such as DDR, HBM, and GDDR, adding value through your prior experience in IP verification. Qualifications Required: - BE/BTech/ME/MTech in Electrical/Electronics/VLSI with a focus on design and verification engineering. - Proficiency in UVM and System Verilog coding for functional verification environment development. - Experience in IP verification of memory IP would be an added advantage. Cadence is a company where meaningful work is done, and where your contributions can make a real impact. Join us in solving challenges that others cannot tackle, and be a part of a team that is shaping the future of technology.