Principal Hardware Verification Engineer

As a Functional Verification Engineer at Cadence, you will have the opportunity to work on cutting-edge technology in an environment that encourages creativity, innovation, and making a real impact. You will join a diverse team of passionate, dedicated, and talented individuals who strive to exceed expectations for customers, communities, and each other every day. Key Responsibilities: - Work on key Palladium technologies including UPF - Take full responsibility and accountability for the quality of releases and features for Palladium emulation technology - Use your expertise as an Electrical, Electronics, or Computer Science Engineer with a strong understanding of HDLs (Verilog and/or VHDL) - Prior experience in Emulation/UPF is a significant advantage - Proficiency in process automation with scripting - Familiarity with SystemVerilog, C++, and UVM - Experience in Functional Verification of complex digital systems, such as SoC Verification, using a Hardware Verification Language (HVL) like SystemVerilog - Explore innovative solutions to overcome challenges and drive successful outcomes Qualifications Required: - Bachelor's degree in any field of Engineering or related discipline - Master's degree in any relevant field is a plus At Cadence, we value our employees' well-being and prioritize career development, learning opportunities, and recognizing success. Join us to contribute to the world of technology and be part of a company that empowers innovation and leadership. As a Functional Verification Engineer at Cadence, you will have the opportunity to work on cutting-edge technology in an environment that encourages creativity, innovation, and making a real impact. You will join a diverse team of passionate, dedicated, and talented individuals who strive to exceed expectations for customers, communities, and each other every day. Key Responsibilities: - Work on key Palladium technologies including UPF - Take full responsibility and accountability for the quality of releases and features for Palladium emulation technology - Use your expertise as an Electrical, Electronics, or Computer Science Engineer with a strong understanding of HDLs (Verilog and/or VHDL) - Prior experience in Emulation/UPF is a significant advantage - Proficiency in process automation with scripting - Familiarity with SystemVerilog, C++, and UVM - Experience in Functional Verification of complex digital systems, such as SoC Verification, using a Hardware Verification Language (HVL) like SystemVerilog - Explore innovative solutions to overcome challenges and drive successful outcomes Qualifications Required: - Bachelor's degree in any field of Engineering or related discipline - Master's degree in any relevant field is a plus At Cadence, we value our employees' well-being and prioritize career development, learning opportunities, and recognizing success. Join us to contribute to the world of technology and be part of a company that empowers innovation and leadership.