Sr Design Engineering Architect

As an RTL Design Engineer for Interface Controller IP development team at Cadence, your role will be focused on PCIe Architect with ARM CPU subsystem architecture. This includes designing memory subsystem, IO, and cache subsystems. You will also be responsible for designing and supporting the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence. Your tasks will involve adding new features to the RTL, collaborating with existing RTL, ensuring cleanliness of various customer configurations during verification regressions, providing customer support, and ensuring the design adheres to LINT and CDC design guidelines. Key Responsibilities: - Designing memory subsystem, IO, and cache subsystems for ARM CPU - Developing and supporting the RTL of PCIe/CXL/IDE/UALink IP solution - Adding new features to the RTL - Collaborating with existing RTL - Ensuring cleanliness of various customer configurations during verification regressions - Providing customer support - Ensuring design compliance with LINT and CDC design guidelines Qualifications Required: - BE/BTech/ME/MTech in Electrical/Electronics/VLSI - 6-16 years of core RTL Design experience using Verilog - System Verilog experience and familiarity with UVM based environment usage/debugging - Experience in architecture and design of CPU subsystem, memory subsystem, IO, and cache subsystems - Experience with PCIe/CXL/IDE is highly desirable - Prior experience in implementing complex protocols is desirable - Knowledge of scripting is an advantage Cadence is focused on impactful work that matters. Join us in solving challenges that others can't. As an RTL Design Engineer for Interface Controller IP development team at Cadence, your role will be focused on PCIe Architect with ARM CPU subsystem architecture. This includes designing memory subsystem, IO, and cache subsystems. You will also be responsible for designing and supporting the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence. Your tasks will involve adding new features to the RTL, collaborating with existing RTL, ensuring cleanliness of various customer configurations during verification regressions, providing customer support, and ensuring the design adheres to LINT and CDC design guidelines. Key Responsibilities: - Designing memory subsystem, IO, and cache subsystems for ARM CPU - Developing and supporting the RTL of PCIe/CXL/IDE/UALink IP solution - Adding new features to the RTL - Collaborating with existing RTL - Ensuring cleanliness of various customer configurations during verification regressions - Providing customer support - Ensuring design compliance with LINT and CDC design guidelines Qualifications Required: - BE/BTech/ME/MTech in Electrical/Electronics/VLSI - 6-16 years of core RTL Design experience using Verilog - System Verilog experience and familiarity with UVM based environment usage/debugging - Experience in architecture and design of CPU subsystem, memory subsystem, IO, and cache subsystems - Experience with PCIe/CXL/IDE is highly desirable - Prior experience in implementing complex protocols is desirable - Knowledge of scripting is an advantage Cadence is focused on impactful work that matters. Join us in solving challenges that others can't.