Sr. Principal Design Engineer

As a candidate for this role at Cadence, you will be responsible for leading and innovating in the field of technology. With a BTech/MTech in Engineering and a minimum of 12 years of experience in the VLSI industry, particularly in Verification, you will play a crucial role in SOC level verification. Your responsibilities will include: - Developing test plans and tests to ensure the quality and reliability of verification processes - Utilizing strong knowledge of SV and UVM to create verification environments using UVM methodology - Developing bus functional models, monitors, checkers, and scoreboards - Driving coverage-driven verification closure to meet project requirements - Leading verification strategy and ensuring high-quality execution of SOCs/Chiplet based SOCs - Mentoring and guiding verification engineers to foster technical excellence - Collaborating effectively with design, architecture, and cross-functional teams to achieve project goals Additionally, it is important that you have experience in the complete SOC level Verification Cycle and possess strong individual contribution capabilities, along with excellent debugging and problem-solving skills. Your ability to work collaboratively and seamlessly with various teams will be essential for success in this role. At Cadence, we are committed to impactful work that pushes the boundaries of technology. Join us in solving challenges that others cannot, and be a part of our mission to make a difference in the world of technology. As a candidate for this role at Cadence, you will be responsible for leading and innovating in the field of technology. With a BTech/MTech in Engineering and a minimum of 12 years of experience in the VLSI industry, particularly in Verification, you will play a crucial role in SOC level verification. Your responsibilities will include: - Developing test plans and tests to ensure the quality and reliability of verification processes - Utilizing strong knowledge of SV and UVM to create verification environments using UVM methodology - Developing bus functional models, monitors, checkers, and scoreboards - Driving coverage-driven verification closure to meet project requirements - Leading verification strategy and ensuring high-quality execution of SOCs/Chiplet based SOCs - Mentoring and guiding verification engineers to foster technical excellence - Collaborating effectively with design, architecture, and cross-functional teams to achieve project goals Additionally, it is important that you have experience in the complete SOC level Verification Cycle and possess strong individual contribution capabilities, along with excellent debugging and problem-solving skills. Your ability to work collaboratively and seamlessly with various teams will be essential for success in this role. At Cadence, we are committed to impactful work that pushes the boundaries of technology. Join us in solving challenges that others cannot, and be a part of our mission to make a difference in the world of technology.