Principal Design Verification Engineer

Roles and Responsibility Develop the architecture for functional verification environments, including reference models and bus-functional monitors and drivers. Write detailed test plans using random techniques and coverage analysis, collaborating with designers to ensure completeness. Debug failures and work with designers to resolve issues, verifying boot code and architecting tools to streamline design of state-of-the-art multi-core SoCs. Transform requirements from engineering teams into software tools that are easy to use and scalable within a highly parallel compute environment. Unit and regression test software tools, contributing to the methodology behind their development. Collaborate with cross-functional teams to identify and prioritize verification requirements. Job Requirements BS/MS in Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware/software development experience (or PhD with 5+ years). Experience with System Verilog, UVM, and scripting languages such as Python or Perl. Strong understanding of Linux OS and good programming skills, especially in C++ and ARM assembly. Understanding of networking protocols is a plus, along with experience in writing detailed test plans and building sophisticated, directed, and random-verification environments. Ability to accept and work with differing opinions, be diligent and detail-oriented, and willing to take initiative and handle assignments independently. Must be able to learn on the fly and work in a fast-paced environment. Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.