Synthesis/STA_Rakesh_Capgemini

STA (Static timing analysis) Engineers: 4 – 15 years Location:bangalore Skills: Experience in Synthesis of complex SoCs block/ top level and writing timing constraints. Experience in formal verification RTL to netlist – to- netlist with DFT constraints. Experience in post-layout STA closure and timing ECOs. Worked in technology nodes 45 nm and below. Knowledge of low -power aware implementation is a plus. Tools: Design compiler, RTL compiler, LEC, CLP, ETS/ PTSI/ GT. Primary Skills: Able to handle Soc/Subsystem and blocklevel synthesis activities , Soc/Subsystem and blocklevel LEC, CLP and timing closure Secondary Skills: Able to handle PTPX and debug CTS issues to balance clocks