Full Chip Physical Verification Engineer

Job Title: Full Chip Physical Verification Engineer Experience: 5+ Years Location: Chennai Job Description We are looking for a Full Chip Physical Verification Engineer with 5+ years of experience in Physical Verification (PV) for complex SoC / Full Chip designs. The candidate should have strong hands-on experience in DRC, LVS, ERC, ANT, and physical signoff checks across advanced technology nodes. Key Responsibilities Perform full chip physical verification activities for SoC / ASIC designs Run and debug DRC, LVS, ERC, ANT, density, and connectivity checks Analyze and resolve PV violations in coordination with PD/Layout teams Work on physical signoff closure for tapeout readiness Support hierarchical and full-chip verification flow Collaborate with Physical Design, Layout, and CAD teams for issue closure Ensure design compliance with foundry rules and signoff requirements Required Skills: Strong experience in Full Chip Physical Verification Hands-on expertise in DRC / LVS / ERC / ANT / Density checks Good understanding of ASIC/SoC physical design flow Experience with Calibre / ICV / Pegasus tools Knowledge of advanced nodes and foundry rule decks Ability to debug and close complex PV issues Good communication and teamwork skills