Std. Cell/ Layout Engineers

Standard Cell Library Development: Design and optimize standard cell libraries containing logic gates (e.g., AND, OR, NAND, NOR, Flip-Flops) with various drive strengths and functionality options. Cell Characterization: Characterize standard cells by performing static timing analysis (STA) to measure delay, power consumption, and other performance metrics under different process corners and operating conditions. Custom Cell Design: Create custom cells or specialized standard cells when needed for unique design requirements. Standard Cell Layout Design: Generate physical layouts for standard cells using layout design tools (e.g., Cadence Virtuoso, Synopsys IC Compiler). DRC and LVS Verification: Run design rule checking (DRC) and layout versus schematic (LVS) verification to ensure that the standard cell layouts adhere to manufacturing design rules and match their schematics. Library Characterization: Characterize and validate the standard cell library for various technology nodes, ensuring consistency and accuracy. Low-Power Design: Implement low-power standard cells with features like power gating and voltage scaling to optimize power consumption. Advanced Process Nodes: Address challenges specific to advanced process nodes, such as FinFET and multi-patterning, when designing and optimizing standard cells. Design for Manufacturability (DFM): Collaborate with manufacturing teams to ensure that standard cell layouts are manufacturable, considering lithography, process variation, and yield. Library Documentation: Maintain detailed documentation of standard cell libraries, including timing models, power models, and layout guidelines. Library Integration: Work with digital design teams to integrate standard cell libraries into the overall chip design.