Architecture - I/O Architect

Architecture: Define NuLink PHY subsystems (physical and logical/link layers) and hierarchical modular protocol bridges between PCIe, AXI4, APB, CHI, CXL (.io/.cache/.mem), DDR to name a few. Definition of a firmware first based hardware architecture approach.

Protocol Design: Design protocol conversion layers with transaction ordering, credit-based flow control, QoS, address translation, coherency management, and memory semantics across protocol domains

Performance Evaluation and Optimization: Model and tune PHY data path, link protocols, and CDC architectures for protocol efficiency, bandwidth, latency, power, and signal integrity. Conduct technical evaluation and benchmark analysis against internal and external IPs.

Collaboration: Partner with ASIC, firmware, and post-silicon teams. Support customer integration for compute-to-memory (CXL/DDR), processor interconnect (AXI/PCIe), and control plane (APB). Create clear and comprehensive architecture specifications with foolproof integration guidelines.

Validation: Review characterization plans for PLL, VCO, ATB, and link training. Create protocol testbenches validating transaction handling, latency, throughput, and compliance

Compliance: Ensure UCIe, PCIe, CXL, AMBA AXI/APB, and DDR specification compliance. Define interoperability requirements and protocol error handling. Be part of industry standards bodies and work groups to keep Eliyan's product implementations up to date with the latest versions of the standards.

Leadership: Mentor engineers on protocol implementation, timing constraints, and hierarchical design. Effectively collaborate with industry technologists, business leaders and ability to network seamlessly with industry peers to influence stakeholders.