PD - Principal, Physical Design

Architecture and packaging driven floorplanning and integration so physical partitions match system and package constraints

Well defined boundaries with lego style pin alignment and consistent interface placement across chip and blocks

Feedthrough, repeater and bus planning with early reservation of routing corridors, layers, and resources for cross block connectivity.

Define clocking architecture methodology selecting spine and rib, H tree, or mesh to optimize power, skew, latency, and robustness.

Establish CTS methodology including skew and latency targets, buffer and ICG strategy, NDR and shielding rules for critical clock routes.

Define skew groups and balancing strategy across library corners, ensuring consistent behavior under MMMC variations and derates.

Drive clock constraint quality across hierarchy with clean chip to block and block to chip handoff for signoff readiness.

Define DRC aware power grid architecture including rings, straps, and mesh, matching metal resistivity assumptions to IR drop targets and EM limits.

Ensure careful planning around analog routing with keepouts, shielding, spacing, and grid topology choices that preserve sensitive nets and meet DRC.

Drive lego aligned power mesh alignment across top level, subsystem, and block level with consistent strap pitch, via patterns, and clean connectivity.

Lead early and signoff EM and IR analysis, identify hotspots, and implement grid reinforcement and via optimization without routing or congestion penalties.

Align power planning with floorplan and package constraints including bump map, current demand, and entry points to minimize noise and IR drop.