Physical Design

Physical Design

2+ years of Physical design experience preferably in 14nm, 10 nm, 7 nm flows, Synthesis using DC, Floorplan, P&R, Physical verification (DRC, LVS), STA & Timing closure, Expert in Synthesis to Tape-out flow, including Layout, DFT, Timing Closure, and Chip Finishing.

Ability to independently handle complex blocks to closure right from Synthesis, Worked on at least 2 end to end projects those spanned across entire life cycle of development, Ability to communicate with architecture, RTL design and other remote teams, Excellent verbal and written communication skills, Performing a wide range of back-end activities, including synthesis of RTL, DFT insertion, power optimization, Floor-planning, PnR (Place and Route), Clock Tree Synthesis (CTS), Timing closure (STA), DRC, LVS, Antenna checks, IR drop (RedHawk), multi voltage checks etc.

Participating in the development of a back-end ASIC design flow.

Experience of UPF low power design through synthesis, place and route. Expertise in Synopsys suite (IC Compiler, Primetime, Design Compiler)

Strong communication and influencing skills required.

Candidate should be good with Synopsys tool Primetime Knowledge of STA Aware of Physical design flow and convergence methodologies 2 years of experience in backend physical design and timing closure is desired ability to code scripts in Perl and TCL.

Work Experience* Physical design, Floorplan, P&R, Physical verification (DRC, LVS), STA & Timing closure, Expert in Synthesis to Tape-out flow

Job type: Direct Placement Reference: 19-00052