Memory Layout Engineer: Bangalore

We are looking for an experienced Memory Layout Engineer with strong expertise in custom layout design, memory leafcell layout, FinFET technology, and physical verification. The ideal candidate should have hands-on experience in designing optimized memory layouts and integrating memory leafcell libraries at the top level. Key Responsibilities & Requirements: Hands-on experience in Memory Layout / Custom Layout Design . Experience in designing Memory Leafcell Layout Libraries from scratch , including top-level integration . Good understanding of different Memory Architectures and Memory Layout Structures . Strong knowledge of optimized layout design techniques for improved performance and area efficiency. Sound knowledge and hands-on experience in FinFET technology and advanced process nodes. Strong understanding of FinFET layout design rules, limitations, and process-related constraints . Proficiency in Physical Verification flow and debugging , including: DRC (Design Rule Check) LVS (Layout Versus Schematic) ERC (Electrical Rule Check) Boundary Condition checks Ability to analyze and resolve complex layout and physical verification issues. Interested can share resume at shubhanshi@incise.in