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About the role
Experience with advanced technology nodes (16nm / 7nm/5nm and below) The ideal candidate should have hands-on experience in DFT architecture,scan insertion,ATPG,MBIST,and JTAG,along with strong knowledge of industry-standard EDA tools. . Key Responsibilities Required Skills Preferred Skills 7+ years of experience in DFT implementation for ASIC / SoC designs
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