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About the role
Job Description: Specify the DFT Architecture including JTAG functionality, boundary scan, Hierarchical scan, at- speed testing, I/ O testing requirements, MBIST and Repair, Implement Test Logic. Generate and debug test patterns BE/ BTECH/ ME/ MTECH in EC/ EE/ CS or related field Exposure to EDA tools viz. DC, LogicVision, Fastscan, Tetramax Good knowledge about all DFT concepts & ATPG Flow. Vector Generation, ATPG Pattern Generation, Validation, Scan insertion and validation, Timing Analysis
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