Physical Design (PD) Engineers

Job Description: Responsible for PD Implementation of complex ASIC/ SoCs Floorplan, Place & Route, SI Avoidance/ fixing, power/ clock distribution, timing closure - timing, power, clock and noise analysis and DRC/ LVS Job Requirements: Must have successful track record taping out complex chips (min 2M gates) Prior experience in design timing closure, Clock/ Power distribution and analysis, RC Extraction, P & R Hands on experience in running STA & Synthesis Should be a power user of P&R and analysis tools from Magma, Cadence or Synapses Coding experience in C , C, Perl and TCL a big plus