Verification Engineer (ENG)

Experience required: • Candidate with hands-on experience on FPGA (where the chip is reprogrammable) and ASIC programming , someone with network domain, or chipset domain experience, • Good experience in Verilog/System Verilog, RTL coding and simulation/synthesis for ASIC/FPGA • Hands on experience with Synopsys simulation tool VCS, Scripting(PERL, Tcl) & knowledge of C/C++. • Exposure to OVM/ UVM verification methodology & knowledge of Networking protocols(PCIe, Gbit Ethernet & High speed serial Interfaces(SERDES).