Functional Verification Engineer

As a Functional Verification Engineer at our company, you will play a crucial role in our cutting-edge silicon design team in Bengaluru. With 710 years of hands-on experience, you will be responsible for architecting and implementing advanced verification environments, driving coverage closure, and collaborating with global teams to deliver world-class silicon solutions. Key Responsibilities: - Architect and implement test benches for complex SoCs. - Define test & coverage plans to ensure robust verification. - Develop constrained random tests and adversarial scenarios. - Specify and analyze functional coverage metrics. - Design and implement reference models for verification. - Automate regression test suites for scalability and efficiency. - Collaborate with architects, logic design, and software engineers in a remote team setup. - Participate in architecture reviews and micro-architecture/code reviews. - Contribute to methodology adoption and best practices within the team. - Provide lab debug and simulation support for silicon bring-up. Qualifications Required: - Strong proficiency in Verilog & SystemVerilog. - Solid verification expertise: planning, problem-solving, debug, adversarial/random testing. - Hands-on experience with UVM & VMM methodologies. - Proven ability to architect test plans and test benches. - Exposure to OTN, Ethernet protocols, PCIe, AXI, I2C, SPI, MDIO, memory controllers is a plus. - Familiarity with VCS simulation flow, coverage analysis, and assertions. If there are any additional details about the company present in the job description, please provide that for a more comprehensive overview. As a Functional Verification Engineer at our company, you will play a crucial role in our cutting-edge silicon design team in Bengaluru. With 710 years of hands-on experience, you will be responsible for architecting and implementing advanced verification environments, driving coverage closure, and collaborating with global teams to deliver world-class silicon solutions. Key Responsibilities: - Architect and implement test benches for complex SoCs. - Define test & coverage plans to ensure robust verification. - Develop constrained random tests and adversarial scenarios. - Specify and analyze functional coverage metrics. - Design and implement reference models for verification. - Automate regression test suites for scalability and efficiency. - Collaborate with architects, logic design, and software engineers in a remote team setup. - Participate in architecture reviews and micro-architecture/code reviews. - Contribute to methodology adoption and best practices within the team. - Provide lab debug and simulation support for silicon bring-up. Qualifications Required: - Strong proficiency in Verilog & SystemVerilog. - Solid verification expertise: planning, problem-solving, debug, adversarial/random testing. - Hands-on experience with UVM & VMM methodologies. - Proven ability to architect test plans and test benches. - Exposure to OTN, Ethernet protocols, PCIe, AXI, I2C, SPI, MDIO, memory controllers is a plus. - Familiarity with VCS simulation flow, coverage analysis, and assertions. If there are any additional details about the company present in the job description, please provide that for a more comprehensive overview.