Lead ASIC RTL Design Engineer

As a highly skilled Lead ASIC RTL Design Engineer with 6-12 years of experience, your role will involve driving the microarchitecture development for complex ASIC/SoC blocks. This includes balancing performance, power, area, and scalability requirements, developing high-quality RTL using Verilog/SystemVerilog, defining datapath, control logic, pipeline architecture, clocking strategies, and state machines. You will collaborate closely with various teams throughout the development cycle, create detailed design specifications, and perform RTL linting, CDC/RDC analysis, low-power checks, and design quality signoff. Additionally, you will support synthesis, timing closure, power optimization, and silicon bring-up activities, as well as analyze and resolve functional, timing, and implementation issues. Key Responsibilities: - Drive microarchitecture development for complex ASIC/SoC blocks - Develop high-quality RTL using Verilog/SystemVerilog - Define datapath, control logic, pipeline architecture, clocking strategies, and state machines - Collaborate closely with cross-functional teams - Create detailed design specifications and implementation plans - Perform RTL linting, CDC/RDC analysis, low-power checks, and design quality signoff - Support synthesis, timing closure, power optimization, and silicon bring-up activities - Analyze and resolve functional, timing, and implementation issues - Drive design reviews and ensure adherence to coding guidelines and design methodologies Qualifications Required: - Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field - 6-12 years of ASIC/SoC RTL Design experience - Strong expertise in digital design fundamentals, computer architecture, and microarchitecture development - Proficiency in Verilog/SystemVerilog RTL design - Experience with pipelined architectures, cache controllers, memory subsystems, interconnects, and high-performance datapaths - Hands-on experience with synthesis, STA concepts, CDC, RDC, lint, and low-power methodologies - Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens EDA - Experience with scripting using Python, Perl, or Tcl for design automation - Strong debugging, problem-solving, and design optimization skills Preferred Skills: - Experience in CPU, GPU, AI/ML Accelerator, Networking, Storage, or High-Speed Interface designs - Knowledge of AMBA AXI/AHB/APB protocols and on-chip interconnect architectures - Exposure to low-power design techniques including UPF/CPF - Understanding of DFT, scan insertion, and silicon validation activities - Experience working on advanced process nodes (7nm, 5nm, 3nm) is a plus Note: Additional details about the company were not present in the provided job description. As a highly skilled Lead ASIC RTL Design Engineer with 6-12 years of experience, your role will involve driving the microarchitecture development for complex ASIC/SoC blocks. This includes balancing performance, power, area, and scalability requirements, developing high-quality RTL using Verilog/SystemVerilog, defining datapath, control logic, pipeline architecture, clocking strategies, and state machines. You will collaborate closely with various teams throughout the development cycle, create detailed design specifications, and perform RTL linting, CDC/RDC analysis, low-power checks, and design quality signoff. Additionally, you will support synthesis, timing closure, power optimization, and silicon bring-up activities, as well as analyze and resolve functional, timing, and implementation issues. Key Responsibilities: - Drive microarchitecture development for complex ASIC/SoC blocks - Develop high-quality RTL using Verilog/SystemVerilog - Define datapath, control logic, pipeline architecture, clocking strategies, and state machines - Collaborate closely with cross-functional teams - Create detailed design specifications and implementation plans - Perform RTL linting, CDC/RDC analysis, low-power checks, and design quality signoff - Support synthesis, timing closure, power optimization, and silicon bring-up activities - Analyze and resolve functional, timing, and implementation issues - Drive design reviews and ensure adherence to coding guidelines and design methodologies Qualifications Required: - Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field - 6-12 years of ASIC/SoC RTL Design experience - Strong expertise in digital design fundamentals, computer architecture, and microarchitecture development - Proficiency in Verilog/SystemVerilog RTL design - Experience with pipelined architectures, cache controllers, memory subsystems, interconnects, and high-performance datapaths - Hands-on experience with synthesis, STA concepts, CDC, RDC, lint, and low-power methodologies - Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens EDA - Experience with scripting using Python, Perl, or Tcl for