Senior Substrate Layout Engineer

Mercury Systems is seeking the best and brightest engineering talent to help us deliver cutting‑edge technology for mission‑critical aerospace and defense applications, advancing innovation where it matters most.

In this role, our team is looking for a Senior Substrate Layout Engineer who will lead complex HDI PCB and substrate layout efforts for advanced microelectronic solutions used in aerospace, defense, and space systems. You will contribute directly to the design, layout, and optimization of rugged, high‑density microelectronics that operate in the harshest environments with exceptional reliability. This role serves as a technical authority within Mercury’s Microsystems business, driving layout excellence, influencing engineering standards, and shaping the technical direction of multiple high‑impact programs. Working within Mercury’s Integrator Mindset, you will collaborate across sites and disciplines to deliver breakthrough microelectronics that strengthen national security and support onshore trusted manufacturing.

Job Responsibilities:

Provide technical leadership focused on high‑speed interfaces and high‑density substrate layout techniques, guiding engineering teams to deliver high‑quality microelectronic solutions

Drive the design, layout, and analysis of complex electrical and mechanical systems, including high‑density interposers, substrates, and PCB layouts supporting digital, analog, power, and RF signals across multiple die (primarily flip‑chip)

Manage high‑speed, multi‑layer packaging activities involving HDI structures, blind and buried vias, BGAs, RF routing, and design‑for‑test (DFT) considerations

Coordinate development processes to ensure alignment with supplier Design for Manufacturing (DFM) rules and capabilities

Create fabrication drawings that accurately represent design intent and collaborate with fabrication suppliers to ensure successful technical transfer

Review artwork, drawings, and design artifacts throughout the layout cycle and during final design reviews for fabrication and assembly

Support multidisciplinary investigations, feasibility studies, and design trades in collaboration with cross‑functional engineering teams

Apply systems‑thinking to understand and communicate how design decisions impact the broader system

Assist the team beyond specific technical discipline as needed to meet program and organizational goals

Required Qualifications:

Bachelor’s or higher degree in engineering in electrical or electronics engineering

Typically requires a minimum of 4 years of experience as a high‑density package layout designer using industry‑standard tools

Proficiency with Cadence APD+ physical and electrical constraint editors and experience with HDI stack‑ups, blind/buried micro‑vias, and fine‑pitch routing (e.g., 15µm/15µm to 2µm/2µm or below)

Knowledge of Cadence Constraint Manager

Experience with 2.5D devices, interposers, substrates, flip‑chip, and high‑end package design

Understanding of layout techniques in digital, analog, and/or RF designs

High‑end package design experience, especially in advanced substrate or interposer designs.

Ability to work within a Cadence schematic/netlist‑driven layout workflow; experience with CAM tools for manufacturing data validation (CAM350 and Blueprint preferred)

Understanding of layout techniques for digital, analog, and RF designs; knowledge of JEDEC and IPC design, fabrication, and assembly specifications

Knowledge of electronic packaging techniques and collaboration with mechanical engineering teams to support 3D modeling for fit checks and thermal analyses

Working knowledge of JEDEC and IPC design, fabrication, and assembly specifications

Experience creating assembly documentation and fabrication deliverables per company and industry standards

“This position requires you to have or obtain a government security clearance. Security clearances may only be granted to U.S. citizens.”

Preferred Qualifications

• Understanding of signal‑integrity fundamentals including impedance, crosstalk, and power‑integrity considerations

• Knowledge of substrate materials, stack‑up creation, and packaging architectures

• Experience with Through‑Silicon Via (TSV) or interposer‑based designs or die stacking

• Familiarity with Ansys or Cadence simulation tools such as Sigrity and Clarity

• Ability to support electrical engineers with netlisting and component‑selection tasks

• Experience routing high‑frequency SERDES or RF interfaces

• Experience with scripting or automation for layout workflows