Physical Design Engineer

Key Responsibilities Physical Implementation: Perform floorplanning, power planning, placement, Clock Tree Synthesis (CTS), and routing for complex, timing-critical blocks or full-chip top-level integration. Signoff Closure: Ensure timing (STA), power integrity, and physical verification (DRC/LVS/ERC/ESD) closure on advanced technology nodes (5nm, 4nm, 3nm). Collaboration: Coordinate with RTL design, STA, and verification teams Requirements & Qualifications Experience: 3–5 years on ASIC physical design. Tools: Strong expertise in Cadence Innovus or Synopsys ICC/ICC2. Technical Knowledge: Deep understanding of Netlist to GDSII flow Education: B.E/B.Tech or M.E/M.Tech in Electronics/Electrical