Source description
About the role
. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Must have worked on cadence tools for layout design and Cadence / Mentor/Synopsys tools for physical verification checks Hands on experience with layouts of important memory building blocks like control,sense amplifiers,I / O Blocks,bit cell array and decoders etc in compiler
More at Pozibility Technologies