DFT Engineer

Key Responsibilities: Implement and verify DFT logic including MBIST, scan chains, scan compression, TAP, iJTAG, and eFuse. Perform scan insertion, ATPG pattern generation, and coverage analysis. Execute MBIST insertion, simulation, and debug at RTL and gate levels. Collaborate with silicon and test engineering teams to create test plans and generate test patterns. Participate in post-silicon bring-up, diagnostics, and characterization activities. Work with EDA and IP vendors to adopt advanced DFT/DFD/DFY methodologies. Integrate DFT/BIST flows into synthesis and ensure timing closure across all stages. Utilize Verilog HDL, simulation, and waveform debugging tools for design verification. Apply strong understanding of clock domain crossings and the impact of DFT on synthesis and physical design. Hands-on experience with Mentor DFT and Synopsys simulation tools is essential.