DV Engineers (Ethernet)

As an ASIC Design Verification Engineer for the Infrastructure organization in Bangalore, you will be responsible for the verification closure of a design module or sub-system. Your role will involve test-planning, UVM based testbench development, and verification closure using approaches like Formal and Emulation to achieve a bug-free design. You will collaborate with various teams towards creating a first-pass silicon success for cutting-edge ASIC solutions for data center applications. Key Responsibilities: - Define and implement IP/SoC verification plans, build verification test benches, and develop functional tests based on the verification test plan - Drive Design Verification to closure based on defined verification metrics, including test plan, functional, and code coverage - Debug, root-cause, and resolve functional failures in the design by partnering with the Design team - Perform simulation-based testing, including functional, performance, and compliance testing - Stay updated with industry trends, standards, and best practices related to Networking - Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams to ensure the highest design quality - Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools, and technologies - Mentor other engineers to deliver high confidence verification for complex ASIC projects Qualifications Required: - Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience - Track record of first-pass success in ASIC development cycles with at least 5 years of relevant experience - Hands-on experience in Verilog, SystemVerilog, UVM, C/C, Python based verification - Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM methodologies - Proficiency in scripting languages such as Python, Perl, or TCL for building tools and flows for verification environments - Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle - Demonstrated experience with effective collaboration with cross-functional teams The job posting has been aggregated from an external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying. As an ASIC Design Verification Engineer for the Infrastructure organization in Bangalore, you will be responsible for the verification closure of a design module or sub-system. Your role will involve test-planning, UVM based testbench development, and verification closure using approaches like Formal and Emulation to achieve a bug-free design. You will collaborate with various teams towards creating a first-pass silicon success for cutting-edge ASIC solutions for data center applications. Key Responsibilities: - Define and implement IP/SoC verification plans, build verification test benches, and develop functional tests based on the verification test plan - Drive Design Verification to closure based on defined verification metrics, including test plan, functional, and code coverage - Debug, root-cause, and resolve functional failures in the design by partnering with the Design team - Perform simulation-based testing, including functional, performance, and compliance testing - Stay updated with industry trends, standards, and best practices related to Networking - Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams to ensure the highest design quality - Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools, and technologies - Mentor other engineers to deliver high confidence verification for complex ASIC projects Qualifications Required: - Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience - Track record of first-pass success in ASIC development cycles with at least 5 years of relevant experience - Hands-on experience in Verilog, SystemVerilog, UVM, C/C, Python based verification - Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM methodologies - Proficiency in scripting languages such as Python, Perl, or TCL for building tools and flows for verification environments - Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle - Demonstrated experience with effective collaboration with cross-functional teams The job posting has been aggregated from an external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.