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About the role
Job Title: Jr. Analog Layout Engineer - 3-5 Yrs Client: AMD Xilinx Location: Hyderabad No. Of positions: 10 Experience required: 3-5 Yrs Key Responsibilities/Preferred Experience: The role involves execution in the field of full custom layouts in cutting edge technology nodes. It will require a good layout electrical parameter knowledge along with quick learning capabilities. Candidate should be able to handle sub cells/leaf cells that are needed to build IP/macro using CAD tools Chip level integration, physical verification and electricals closure Candidate will be exposed/experienced to various other fields of custom layout Custom layout expertise in lower technology Digital, Analog and mixed signal layout. Good understanding of reliability concepts Good understating of layout electrical parameters and closure Required experience 3-5 years Note: This is for Analog Layout Engineers having exp in custom block layout like PLL, Bandgap, ADC, DAC etc. and Virtuoso, Calibre, DRC, LV Requires TSMC 3nm and 2nm 3-way NDA in place (Please ensure you have a valid NDA) Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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