PD- Lead with AMD experience

Job Title: PD- Lead with AMD experience (8-15 Yrs) Experience: 8+-15 Years Location: Hyderabad Job Description We are seeking an experienced Physical Design (PD) Engineer with 8+ years of hands-on ASIC implementation experience. The ideal candidate will have prior experience at AMD and a strong background in delivering high-performance, complex SoC designs across advanced technology nodes. Key Responsibilities Own and drive end-to-end physical design flow from floorplanning to GDSII Perform chip and block-level floorplanning , power planning, and placement Lead timing closure including setup, hold, and clock optimization Execute CTS , routing, and physical optimization for performance, power, and area (PPA) Perform physical verification and signoff including DRC, LVS, IR drop, EM, and noise analysis Collaborate closely with RTL, STA, DFT, and circuit design teams Debug and resolve complex physical and timing issues in high-frequency designs Contribute to methodology improvements and best practices for PD flows Mentor junior engineers and provide technical guidance as needed Required Qualifications Bachelor s or Master s degree in Electrical Engineering or related field 8+ years of experience in ASIC Physical Design Prior experience at AMD (preferred/required) Strong expertise in advanced technology nodes (7nm, 5nm, 3nm preferred) Proven experience with timing closure on high-performance designs Solid understanding of power integrity, signal integrity, and clocking Hands-on experience with industry-standard EDA tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, etc.) Strong scripting skills in Tcl, Perl, or Python Preferred Qualifications: Experience with CPU, GPU, or high-performance SoC designs Familiarity with multi-die / chiplet-based designs Knowledge of low-power design techniques (UPF, power gating) Experience working in fast-paced, tapeout-driven environments