Design Verification Engineer, High-Bandwidth Memory

As a Verification Engineer at Silicon Patterns, you will be responsible for the end-to-end verification of the HBM controller subsystem across multiple protocol layers, focusing on HBM2, HBM2E, and HBM3 protocols. Your key responsibilities will include: - Authoring and maintaining HBM controller subsystem verification plans - Covering all protocol layers including PHY interface, DRAM controller, AXI/CHI host interface, power management, and RAS features - Developing and executing SystemVerilog/UVM-based testbenches - Creating test cases, sequences, assertions, and coverage models - Performing functional and protocol-level verification for HBM designs - Analyzing and debugging simulation failures and performance issues - Achieving coverage closure (functional and code coverage) - Collaborating with RTL, architecture, and system teams To excel in this role, you should have: - Strong experience in HBM2, HBM2E, and HBM3 protocol verification - Proficiency in SystemVerilog (SV) and UVM methodology - Experience in subsystem/IP-level verification - Solid understanding of memory controller architecture - Knowledge of AXI or CHI protocols - Experience with assertion-based verification (SVA) - Hands-on experience with simulation/debug tools like VCS, Questa, Xcelium - Strong debugging and analytical skills Preferred qualifications include: - Experience in high-speed memory interfaces or SoC verification - Understanding of power management and RAS features - Exposure to formal verification is a plus - Good communication and teamwork abilities Silicon Patterns offers you the opportunity to work on advanced HBM3 memory technologies, contribute to cutting-edge semiconductor designs, and be part of a collaborative and growth-focused environment. If you are interested in this exciting opportunity, please share your CV at shalini@siliconpatterns.com. As a Verification Engineer at Silicon Patterns, you will be responsible for the end-to-end verification of the HBM controller subsystem across multiple protocol layers, focusing on HBM2, HBM2E, and HBM3 protocols. Your key responsibilities will include: - Authoring and maintaining HBM controller subsystem verification plans - Covering all protocol layers including PHY interface, DRAM controller, AXI/CHI host interface, power management, and RAS features - Developing and executing SystemVerilog/UVM-based testbenches - Creating test cases, sequences, assertions, and coverage models - Performing functional and protocol-level verification for HBM designs - Analyzing and debugging simulation failures and performance issues - Achieving coverage closure (functional and code coverage) - Collaborating with RTL, architecture, and system teams To excel in this role, you should have: - Strong experience in HBM2, HBM2E, and HBM3 protocol verification - Proficiency in SystemVerilog (SV) and UVM methodology - Experience in subsystem/IP-level verification - Solid understanding of memory controller architecture - Knowledge of AXI or CHI protocols - Experience with assertion-based verification (SVA) - Hands-on experience with simulation/debug tools like VCS, Questa, Xcelium - Strong debugging and analytical skills Preferred qualifications include: - Experience in high-speed memory interfaces or SoC verification - Understanding of power management and RAS features - Exposure to formal verification is a plus - Good communication and teamwork abilities Silicon Patterns offers you the opportunity to work on advanced HBM3 memory technologies, contribute to cutting-edge semiconductor designs, and be part of a collaborative and growth-focused environment. If you are interested in this exciting opportunity, please share your CV at shalini@siliconpatterns.com.