Verification Lead

Role Overview: As a PCIe Verification Engineer in Bangalore with 5+ years of experience, you will be responsible for developing UVM-based testbench and verification environments while having a deep understanding of the PCIe protocol. Your main tasks will include creating test plans, test cases, sequences, and coverage models, as well as performing protocol-level verification for PCIe layers such as PHY, DLL, and TL. You will also be debugging issues using waveforms, logs, and assertions, and working on regression, coverage closure, and sign-off activities. Key Responsibilities: - Develop UVM-based testbench & verification environments - Create test plans, test cases, sequences & coverage models - Perform protocol-level verification (PCIe layers PHY, DLL, TL) - Debug issues using waveforms, logs & assertions - Work on regression, coverage closure & sign-off activities Qualification Required: - Strong expertise in SystemVerilog & UVM - Hands-on experience in PCIe (Gen3/4/5/6) - Experience in testbench development & debugging - Good understanding of digital design concepts - Exposure to simulation tools (VCS / Questa / Xcelium) Additional Details: The company is looking for candidates who also have experience with SoC/Sub-system level verification, scripting knowledge (Python / Perl / TCL), and knowledge of C/C++ or assembly-based testing. Please feel free to share your CV for further consideration. Role Overview: As a PCIe Verification Engineer in Bangalore with 5+ years of experience, you will be responsible for developing UVM-based testbench and verification environments while having a deep understanding of the PCIe protocol. Your main tasks will include creating test plans, test cases, sequences, and coverage models, as well as performing protocol-level verification for PCIe layers such as PHY, DLL, and TL. You will also be debugging issues using waveforms, logs, and assertions, and working on regression, coverage closure, and sign-off activities. Key Responsibilities: - Develop UVM-based testbench & verification environments - Create test plans, test cases, sequences & coverage models - Perform protocol-level verification (PCIe layers PHY, DLL, TL) - Debug issues using waveforms, logs & assertions - Work on regression, coverage closure & sign-off activities Qualification Required: - Strong expertise in SystemVerilog & UVM - Hands-on experience in PCIe (Gen3/4/5/6) - Experience in testbench development & debugging - Good understanding of digital design concepts - Exposure to simulation tools (VCS / Questa / Xcelium) Additional Details: The company is looking for candidates who also have experience with SoC/Sub-system level verification, scripting knowledge (Python / Perl / TCL), and knowledge of C/C++ or assembly-based testing. Please feel free to share your CV for further consideration.