Design Validation Engineer - Electronic

Design Verification Engineer DDR5 / LPDDR5 | SystemVerilog | UVMExperience : 7-10 Years (Minimum 3 years of hands-on DDR/LPDDR protocol verification experience)Job Location : Bengaluru | Visakhapatnam (Vizag) | Kochi | AhmedabadEmployment Type : Full-TimeJob Summary : We are looking for an experienced Design Verification Engineer with strong expertise in DDR5/LPDDR5 memory protocol verification for complex ASIC/SoC designs. The ideal candidate should have hands-on experience in SystemVerilog, UVM, and memory subsystem verification, with a minimum of 3 years of DDR/LPDDR verification experience. You will work closely with Design, Architecture, and Validation teams to develop robust verification environments, validate memory controller functionality, and ensure first-pass silicon success.Collaborate with Design, Architecture, and Physical Design teams to resolve verification issues.- Participate in design reviews and contribute to verification methodology improvements.Required Skills : - 710 years of experience in ASIC/SoC Design Verification.- Minimum 3 years of hands-on experience in DDR/LPDDR memory protocol verification.- Excellent programming skills in SystemVerilog (SV).- Strong hands-on experience with UVM (Universal Verification Methodology).- Experience in developing reusable verification environments and constrained-random verification.- Experience with functional coverage, assertions, and regression execution.- Preferred Skills : - Experience leading verification teams or owning verification projects.- Experience with scripting using Python, Perl, or Shell.- Education : - B.E./B.Tech/M.Tech in Electrical Engineering, Electronics & Communication, VLSI, Microelectronics, or a related discipline. ( .