Electronic Design Engineer / Hardware Engineer

As a Hardware Design Engineer 3 specializing in Physical Design (PnR) in Hyderabad, you will be responsible for supporting the Flow and Methodology team in the implementation of advanced-node semiconductor designs. Your expertise in Place & Route (PnR) methodologies will be crucial in enabling efficient design closure and methodology deployment across leading-edge technology nodes like 6nm, 3nm, and 2nm. Your role will involve collaborating with various teams to optimize PnR workflows and drive PPA optimization. Key Responsibilities: - Support Place & Route workflows for advanced technology nodes such as 6nm, 3nm, and 2nm designs. - Qualify and deploy new EDA tool versions, methodologies, and workflow enhancements. - Evaluate, benchmark, and validate new tool capabilities and flow improvements. - Execute and support multiple PnR design blocks for benchmarking, performance evaluation, and methodology validation. - Collaborate with design, methodology, and CAD teams to enhance design convergence and productivity. - Develop and maintain automation scripts to enhance workflow efficiency and scalability. - Troubleshoot implementation issues and provide technical support for physical design execution teams. Qualification Required: - 6+ years of experience in Physical Design and Place & Route implementation. - Strong hands-on expertise with Synopsys Fusion Compiler, Cadence Innovus, and Cadence Cerebrus. - Solid understanding of advanced-node implementation methodologies and design closure techniques. - Proficiency in scripting and automation using TCL, Perl, and Python. - Experience with PPA optimization, design correlation, and signoff methodologies. - Familiarity with EMIR analysis and signoff validation processes. - Educational Qualifications: B.E./B.Tech./M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or related field. The company seeks candidates with strong hands-on Physical Design execution experience, especially in Place & Route methodologies, and a mandatory requirement for experience with TSMC 3nm and/or 2nm technology nodes. Additionally, experience in supporting Flow and Methodology teams, working with large-scale SoC implementation projects, and exposure to advanced TSMC technology nodes is highly preferred. As a Hardware Design Engineer 3 specializing in Physical Design (PnR) in Hyderabad, you will be responsible for supporting the Flow and Methodology team in the implementation of advanced-node semiconductor designs. Your expertise in Place & Route (PnR) methodologies will be crucial in enabling efficient design closure and methodology deployment across leading-edge technology nodes like 6nm, 3nm, and 2nm. Your role will involve collaborating with various teams to optimize PnR workflows and drive PPA optimization. Key Responsibilities: - Support Place & Route workflows for advanced technology nodes such as 6nm, 3nm, and 2nm designs. - Qualify and deploy new EDA tool versions, methodologies, and workflow enhancements. - Evaluate, benchmark, and validate new tool capabilities and flow improvements. - Execute and support multiple PnR design blocks for benchmarking, performance evaluation, and methodology validation. - Collaborate with design, methodology, and CAD teams to enhance design convergence and productivity. - Develop and maintain automation scripts to enhance workflow efficiency and scalability. - Troubleshoot implementation issues and provide technical support for physical design execution teams. Qualification Required: - 6+ years of experience in Physical Design and Place & Route implementation. - Strong hands-on expertise with Synopsys Fusion Compiler, Cadence Innovus, and Cadence Cerebrus. - Solid understanding of advanced-node implementation methodologies and design closure techniques. - Proficiency in scripting and automation using TCL, Perl, and Python. - Experience with PPA optimization, design correlation, and signoff methodologies. - Familiarity with EMIR analysis and signoff validation processes. - Educational Qualifications: B.E./B.Tech./M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or related field. The company seeks candidates with strong hands-on Physical Design execution experience, especially in Place & Route methodologies, and a mandatory requirement for experience with TSMC 3nm and/or 2nm technology nodes. Additionally, experience in supporting Flow and Methodology teams, working with large-scale SoC implementation projects, and exposure to advanced TSMC technology nodes is highly preferred.