Design Verification Engineer Core and Subsystem

You are a highly skilled Design Verification (DV) Engineer with over 5 years of experience, specializing in core components and complex subsystems. Your expertise includes hands-on experience in DDRSS and Cache Controller verification, along with deep technical and debugging proficiency. Your key responsibilities will include: - Working on standard DV profiles with a focus on DDRSS. - Contributing to the verification of core components and complex subsystems. - Developing and executing test plans, test benches, and verification environments. - Utilizing advanced debugging techniques to identify and resolve design and verification issues. - Collaborating with design and architecture teams to ensure comprehensive coverage and validation. To excel in this role, you must possess: - Strong experience in Cache Controller and complex subsystem verification. - Proficiency in core and subsystem areas. - Excellent debugging skills and problem-solving ability. - Experience in working with standard verification methodologies (UVM/OVM/SystemVerilog) is preferred. - Exposure to memory interfaces (DDRSS) is a must. (Note: No additional details of the company were mentioned in the provided job description.) You are a highly skilled Design Verification (DV) Engineer with over 5 years of experience, specializing in core components and complex subsystems. Your expertise includes hands-on experience in DDRSS and Cache Controller verification, along with deep technical and debugging proficiency. Your key responsibilities will include: - Working on standard DV profiles with a focus on DDRSS. - Contributing to the verification of core components and complex subsystems. - Developing and executing test plans, test benches, and verification environments. - Utilizing advanced debugging techniques to identify and resolve design and verification issues. - Collaborating with design and architecture teams to ensure comprehensive coverage and validation. To excel in this role, you must possess: - Strong experience in Cache Controller and complex subsystem verification. - Proficiency in core and subsystem areas. - Excellent debugging skills and problem-solving ability. - Experience in working with standard verification methodologies (UVM/OVM/SystemVerilog) is preferred. - Exposure to memory interfaces (DDRSS) is a must. (Note: No additional details of the company were mentioned in the provided job description.)