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About the role
You will be responsible for: - Understanding Specs and Standards and developing relevant test plans - Utilizing monitors, scoreboards, sequencers, and sequences that utilize scripts, System Verilog, UVM, and methodologies to increase the rate at which bugs are found and resolved - Demonstrating a thorough understanding of Digital design concepts - Applying thorough understanding of DV methodologies and tools - Having a good understanding of PCIe and CXL protocols (added advantage) - Understanding Bus protocols like AHB/AXI/ACE/ACE-Lite/CHI Qualifications required: - Strong understanding of Specs and Standards - Proficiency in developing test plans - Knowledge of System Verilog, UVM, and DV methodologies - Familiarity with PCIe and CXL protocols is a plus - Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite/CHI (Note: No additional details of the company were mentioned in the provided job description.) You will be responsible for: - Understanding Specs and Standards and developing relevant test plans - Utilizing monitors, scoreboards, sequencers, and sequences that utilize scripts, System Verilog, UVM, and methodologies to increase the rate at which bugs are found and resolved - Demonstrating a thorough understanding of Digital design concepts - Applying thorough understanding of DV methodologies and tools - Having a good understanding of PCIe and CXL protocols (added advantage) - Understanding Bus protocols like AHB/AXI/ACE/ACE-Lite/CHI Qualifications required: - Strong understanding of Specs and Standards - Proficiency in developing test plans - Knowledge of System Verilog, UVM, and DV methodologies - Familiarity with PCIe and CXL protocols is a plus - Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite/CHI (Note: No additional details of the company were mentioned in the provided job description.)
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