DV Engineers (Ethernet)

As an ASIC Design Verification Engineer for the Infrastructure organization at TekWissen, you will work on building IP and System On Chip (SoC) for data center applications. Your responsibilities will include: - Being part of a dynamic team focused on developing innovative ASIC solutions for data center applications - Leading the verification closure of a design module or sub-system from test-planning to verification closure - Utilizing approaches like Formal and Emulation in addition to traditional simulation for bug-free design - Partnering and collaborating with full stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams towards achieving first-pass silicon success Your specific responsibilities as an ASIC DV Engineer, Networking will involve: - Defining and implementing IP/SoC verification plans - Developing functional tests based on verification test plans - Driving Design Verification to closure based on defined verification metrics - Debugging and resolving functional failures in the design - Performing simulation-based testing including functional, performance, and compliance testing - Staying updated with industry trends, standards, and best practices related to Networking - Collaborating with cross-functional teams towards ensuring the highest design quality - Mentoring other engineers to drive high confidence verification for complex ASIC projects Qualifications required for this role include: - Bachelors degree in Computer Science, Computer Engineering, or relevant technical field - At least 5 years of relevant experience in ASIC development cycles - Hands-on experience in Verilog, SystemVerilog, UVM, C/C, Python based verification - Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM methodologies - Experience in areas like RDMA, PCIe, SRIO & Ethernet, and more - Proficiency in scripting languages such as Python, Perl, or TCL - Demonstrated experience with effective collaboration with cross-functional teams Preferred qualifications include experience in developing UVM based verification environments from scratch, development of fully automated flows and scripts for data exploration, and verification of high-speed interfaces like Ethernet, PCIe, DDR, HBM. With 5-10 years of experience, you will have the opportunity to work with TekWissen, an equal opportunity employer supporting workforce diversity. As an ASIC Design Verification Engineer for the Infrastructure organization at TekWissen, you will work on building IP and System On Chip (SoC) for data center applications. Your responsibilities will include: - Being part of a dynamic team focused on developing innovative ASIC solutions for data center applications - Leading the verification closure of a design module or sub-system from test-planning to verification closure - Utilizing approaches like Formal and Emulation in addition to traditional simulation for bug-free design - Partnering and collaborating with full stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams towards achieving first-pass silicon success Your specific responsibilities as an ASIC DV Engineer, Networking will involve: - Defining and implementing IP/SoC verification plans - Developing functional tests based on verification test plans - Driving Design Verification to closure based on defined verification metrics - Debugging and resolving functional failures in the design - Performing simulation-based testing including functional, performance, and compliance testing - Staying updated with industry trends, standards, and best practices related to Networking - Collaborating with cross-functional teams towards ensuring the highest design quality - Mentoring other engineers to drive high confidence verification for complex ASIC projects Qualifications required for this role include: - Bachelors degree in Computer Science, Computer Engineering, or relevant technical field - At least 5 years of relevant experience in ASIC development cycles - Hands-on experience in Verilog, SystemVerilog, UVM, C/C, Python based verification - Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM methodologies - Experience in areas like RDMA, PCIe, SRIO & Ethernet, and more - Proficiency in scripting languages such as Python, Perl, or TCL - Demonstrated experience with effective collaboration with cross-functional teams Preferred qualifications include experience in developing UVM based verification environments from scratch, development of fully automated flows and scripts for data exploration, and verification of high-speed interfaces like Ethernet, PCIe, DDR, HBM. With 5-10 years of experience, you will have the opportunity to work with TekWissen, an equal opportunity employer supporting workforce diversity.