DV Engineers (Ethernet) - 5-10 Yrs

Job Title: DV Engineers (Ethernet) - 5-10 Yrs No. Of Positions: 10 Work Location: Bangalore / Hyderabad Job Description ASIC Design Verification Engineer for the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC DV Engineer, Networking Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan.Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the Design teamPerform simulation-based testing, including functional, performance, and compliance testingStay up-to-date with industry trends, standards, and best practices related to NetworkingCollaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design qualityDevelop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industryMentor other engineers to drive and deliver high confidence verification for highly complex ASIC projects. Minimum Qualifications Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.Track record of first-pass success in ASIC development cyclesAt least 5 years of relevant experienceHands-on experience in Verilog, SystemVerilog, UVM , C/C, Python based verificationExperience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologiesExperience in one or more of the following areas along with functional verification - RDMA, PCIe, SRIO & Ethernet, 400G Mac, RDMA, TSO, LRO, PSP,ROCE (RDMA over converged Ethernet), Congestion Control etcExperience with Design verification of Data-center applications like Video, AI/ML and Networking designsExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycleExperience in IP, Cluster and SoC level verification in both RTL and Gate Level SetupProficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environmentsExperience using analytical skills to craft novel solutions to tackle industry-level complex designsDemonstrated experience with effective collaboration with cross functional teams Preferred Qualifications Experience in development of UVM based verification environments from scratchExperience with development of fully automated flows and scripts for data exploration, analysis and performance verificationExperience with IP or integration verification of high-speed interfaces like Ethernet, PCIe, DDR, HBMExperience with verification of ARM/RISC-V based sub-systems or SoCsExperience in one or more of the following areas along with functional verification - SV Assertions, Formal, EmulationExperience with revision control systems like Mercurial(Hg), Git or SVNExperience with simulators and waveform debugging toolsExperience working across and building relationships with cross-functional design, model and emulation teams Job Title: DV Engineers (Ethernet) - 5-10 Yrs No. Of Positions: 10 Work Location: Bangalore / Hyderabad Job Description ASIC Design Verification Engineer for the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon su