Sr. Staff, Design Verification - CPU Cluster / SoC

You will be working as a RISC-V CPU Cluster/SoC DV Engineer at Tenstorrent, a company leading the industry in cutting-edge AI technology. Your role will involve architecting, developing, and evolving world-class verification infrastructure for high-performance RISC-V CPU clusters. You will have the opportunity to build from scratch, innovate on methodology, and collaborate with top-tier CPU designers. Key Responsibilities: - Build robust verification environments using SystemVerilog, UVM, and C++, and independently define and drive verification plans. - Integrate multiple IPs into clusters or SoCs and verify their interactions with a system-level mindset. - Plan stimuli, use debug techniques, and achieve coverage closure for verifying complex hardware subsystems like caches, NoCs, and memory hierarchies. - Work on features spanning multiple IPs, such as coherence and security, ensuring correct behavior at the cluster or SoC level. Qualifications Required: - Bachelors or Masters degree in Electrical Engineering, Computer Science, or a related field. - Strong experience with System Verilog and UVM-based verification. - Ability to lead subsystem or SoC-level DV projects with integration and system feature validation responsibilities. - Familiarity with AXI/CHI protocols, System IPs flows, and integration flows for multi-IP verification environments. As a member of the Tenstorrent team, you will have the opportunity to learn techniques to scale DV infrastructure for verifying high-performance RISC-V clusters and SoCs. You will also gain experience in verifying multi-agent interactions across CPUs, system IPs, and NoC or fabric components, as well as best practices for cross-IP feature convergence and collaboration with global teams. Tenstorrent offers a highly competitive compensation package and benefits, and is an equal opportunity employer. Please note that eligibility to access U.S. export-controlled technology is required for this position, and any offer of employment will be contingent upon compliance with U.S. export laws. You will be working as a RISC-V CPU Cluster/SoC DV Engineer at Tenstorrent, a company leading the industry in cutting-edge AI technology. Your role will involve architecting, developing, and evolving world-class verification infrastructure for high-performance RISC-V CPU clusters. You will have the opportunity to build from scratch, innovate on methodology, and collaborate with top-tier CPU designers. Key Responsibilities: - Build robust verification environments using SystemVerilog, UVM, and C++, and independently define and drive verification plans. - Integrate multiple IPs into clusters or SoCs and verify their interactions with a system-level mindset. - Plan stimuli, use debug techniques, and achieve coverage closure for verifying complex hardware subsystems like caches, NoCs, and memory hierarchies. - Work on features spanning multiple IPs, such as coherence and security, ensuring correct behavior at the cluster or SoC level. Qualifications Required: - Bachelors or Masters degree in Electrical Engineering, Computer Science, or a related field. - Strong experience with System Verilog and UVM-based verification. - Ability to lead subsystem or SoC-level DV projects with integration and system feature validation responsibilities. - Familiarity with AXI/CHI protocols, System IPs flows, and integration flows for multi-IP verification environments. As a member of the Tenstorrent team, you will have the opportunity to learn techniques to scale DV infrastructure for verifying high-performance RISC-V clusters and SoCs. You will also gain experience in verifying multi-agent interactions across CPUs, system IPs, and NoC or fabric components, as well as best practices for cross-IP feature convergence and collaboration with global teams. Tenstorrent offers a highly competitive compensation package and benefits, and is an equal opportunity employer. Please note that eligibility to access U.S. export-controlled technology is required for this position, and any offer of employment will be contingent upon compliance with U.S. export laws.