Design Verification Engineer with Ethernet 40GB

Job Description: - You will be responsible for Design Verification (DV) using Universal Verification Methodology (UVM), SystemVerilog (SV), and Ethernet. - The work location for this role is Hyderabad/Bangalore. - Your primary focus will be on IP DV with Ethernet MAC. Please share your resume to the provided email address for further consideration. Regards, Jaya Job Description: - You will be responsible for Design Verification (DV) using Universal Verification Methodology (UVM), SystemVerilog (SV), and Ethernet. - The work location for this role is Hyderabad/Bangalore. - Your primary focus will be on IP DV with Ethernet MAC. Please share your resume to the provided email address for further consideration. Regards, Jaya