Source description
About the role
6 to 10 years of experience in ASIC Design Strong Digital Design Knowledge RTL coding experience - System Verilog/Verilog/VHDL Working knowledge in CDC, Linting Experience in Synthesis/STA/DFT/Layout logs/reports review Knowledge in DDR preferable Debug skill of issues
vlsi design,asic design,system verilog,synthesis,rtl coding,digital design,cdc,linting,layout,sta
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