Analog Designer

Have full ownership of IP, its major blocks or sub blocks Support marketing on presales activities technically Be the interface to the customer in technical interactions, feasibility analysis, design reviews, parameter estimations (like Power/Area etc.) Pair with similar domain experts across other geographical locations on core technical initiatives Define the architecture and uArchitecture of the IP’s and its sub functions Understand and disseminate applicable standards and its relevance in a given project to the team Responsible to develop and design the high speed circuit blocks. Design, simulate and characterize high performance CMOS data communication circuits (drivers, receive equalizers, PLLs, high speed samplers, clock recovery circuits). Responsible for Receiver, transmitter or PLL level designs and top level ownership. The designer will be responsible for all aspects of designs such as schematic capture, layout review, simulation & analysis of critical electrical and timing parameters, documentation and silicon bring-up. Will be responsible to work with the system engineering team for Silicon bring up and Characterization. Mentoring of junior designers where applicable. Qualifications BE/BTECH/MTECH Experience in Analog/Mixed signal circuit design focusing on Very High Speed PHYs Strong experience on FinFet technologies required Should possess minimum 3 years of experience working on Memory PHYs Candidates with experience on GDDR/LPDDR/DDR/HBM PHY development would be preferred