Mid-Level SoC Design Verification Engineer

As a Mid-Level SoC Design Verification Engineer, your role will involve verifying ARM-based SoC subsystems and integrations. You will be responsible for developing DV test plans, test benches, and test cases. Additionally, you will build SystemVerilog/UVM verification environments, perform functional verification, and ensure coverage closure. Your duties will also include debugging simulation and integration issues, working with AXI/AHB/APB-based subsystem verification, and supporting gate-level simulation and low-power verification. Collaboration with architecture, RTL, and ATE teams will be essential, along with generating VCD/FSDB files for power analysis and testing. Key Responsibilities: - Verify ARM-based SoC subsystems and integrations - Develop DV test plans, test benches, and test cases - Build SystemVerilog/UVM verification environments - Perform functional verification and coverage closure - Debug simulation and integration issues - Work with AXI/AHB/APB-based subsystem verification - Support gate-level simulation and low-power verification - Collaborate with architecture, RTL, and ATE teams - Generate VCD/FSDB files for power analysis and testing Qualifications Required: - Bachelor's/Master's degree in Electronics, Electrical, or Computer Engineering - 6-8 years of SoC/ASIC verification experience - Strong expertise in ARM architecture and AMBA protocols - Hands-on experience with Arm Corestone platforms - Good experience in SystemVerilog and UVM - Familiarity with Cadence simulation tools - Strong debugging and verification skills No additional company details are mentioned in the job description. As a Mid-Level SoC Design Verification Engineer, your role will involve verifying ARM-based SoC subsystems and integrations. You will be responsible for developing DV test plans, test benches, and test cases. Additionally, you will build SystemVerilog/UVM verification environments, perform functional verification, and ensure coverage closure. Your duties will also include debugging simulation and integration issues, working with AXI/AHB/APB-based subsystem verification, and supporting gate-level simulation and low-power verification. Collaboration with architecture, RTL, and ATE teams will be essential, along with generating VCD/FSDB files for power analysis and testing. Key Responsibilities: - Verify ARM-based SoC subsystems and integrations - Develop DV test plans, test benches, and test cases - Build SystemVerilog/UVM verification environments - Perform functional verification and coverage closure - Debug simulation and integration issues - Work with AXI/AHB/APB-based subsystem verification - Support gate-level simulation and low-power verification - Collaborate with architecture, RTL, and ATE teams - Generate VCD/FSDB files for power analysis and testing Qualifications Required: - Bachelor's/Master's degree in Electronics, Electrical, or Computer Engineering - 6-8 years of SoC/ASIC verification experience - Strong expertise in ARM architecture and AMBA protocols - Hands-on experience with Arm Corestone platforms - Good experience in SystemVerilog and UVM - Familiarity with Cadence simulation tools - Strong debugging and verification skills No additional company details are mentioned in the job description.