Senior Principal Engineer -RTL

. Bachelors degree in Computer Science,Electrical Engineering,or related fields Experience with interconnect fabrics such as Arm and Arteris fabrics,AXI / APB protocols,and NoC architecture Minimum 18 years of experience in Verilog / System Verilog RTL coding with System Verilog assertions These tools must not be used to record,assist with,or enhance responses in any way