Senior Staff Engineer, RTL ASIC Design

We are looking for a highly motivated RTL Design Engineer with 8 to 14 years of experience to architect and deliver next-generation UCIe and high-speed mixed signal IP . Strong domain expertise in high-speed protocols such as UCIe,Ethernet,DDR,PCIe,USB (direct UCIe experience strongly preferred). . Extensive hands-on experience with SystemVerilog / Verilog (VHDL a plus).