DV - Principal Digital Verification Engineer

Provide technical verification leadership to Eliyan products and provide guidance to junior engineers.

Develop and execute verification plans for connectivity IPs and Chiplets .

Create and maintain SystemVerilog/UVM-based verification environments .

Write and debug SystemVerilog/UVM compliant test cases for block and chip level.

Maintain a regression environment for enabling design CI/CD pipelines.

Collaborate with design engineers to ensure design quality with continuous micro-architecture, test-plan, and coverage reviews.

Develop, maintain, and track various test plan items and progress towards RTL freeze.

Stay up to date with industry trends, emerging technologies and progress in standards’ bodies.

Ensure IP compliance with industry standard protocols.

Integration of 3 rd party VIPs and coordinate feature/bug tracking requests.

Perform in the capacity of a technical leader for junior verification engineers.

Create, improve, maintain DPI based FW simulation environments.

Create, improve, maintain gate level simulation environments for functional and power simulations.

Drive state of art verification methodologies for silicon verification including constrained based random verification, coverage driven verification.

Create microcontroller sub system testbenches and verification plan.

Own end-to-end verification for the company products.

Automation of verification flows including automated regression flow