PD - Sr Staff - Physical Verification Lead | Signoff & DRC

KEY RESPONSIBILITIES

Signoff Physical Verification — Top Level

Own end-to-end physical verification signoff strategy from block level through chip top, ensuring all DRC, LVS, ERC, and antenna violations are cleanly resolved before tapeout.

Define and execute hierarchical DRC methodology across multiple abstraction levels (block, partition, top), leveraging Calibre or IC Validator in hierarchical and distributed modes.

Drive full-chip DRC convergence across advanced nodes including 28nm, 22nm, 14nm, 7nm, 5nm, 3nm, and 2nm at Intel, TSMC, Samsung, and GlobalFoundries.

Develop waiver management processes with foundry sign-off teams; distinguish hard violations from soft DFM advisories and document justifications for each waiver class.

Collaborate with physical design teams on real-time DRC closure, guiding routing rules, spacing constraints, and metal fill strategies to minimize violations upstream.

Lead bump planning for flip-chip and 2.5D/3D chiplet assemblies — define bump array configuration, pitch, UBM sizing, and RDL routing to satisfy both electrical and mechanical requirements.

Execute top-level bump DRC checks including bump pitch, clearance, RDL spacing, keep-out zones, and passivation opening rules per foundry and OSAT PDK requirements.

Validate bump-to-bump, bump-to-signal, and bump-to-power domain spacing across multiple power domains and IO ring configurations.

Collaborate with package and substrate teams on co-design constraints to align die-side bump map with package-side ball grid array (BGA) and interposer routing.

Ensure compliance with electromigration (EM) limits on bump current density and perform IR-drop correlation between die and package.

Develop and maintain Calibre SVRF/TVF and IC Validator runsets customized per foundry PDK, managing layer name mappings, derived layers, and rule deck versioning.

Implement incremental and cell-level DRC methodologies to accelerate design iteration turnaround — reducing full-chip DRC runtime by leveraging hierarchical cell reuse.

Drive LVS signoff at all levels of the design hierarchy, establishing schematic-vs-layout equivalence across mixed-signal, standard cell, memory, and custom analog blocks.

Own ERC (Electrical Rules Check) signoff including antenna, floating gate, and latch-up checks across full-chip context.

Lead DFM signoff including critical area analysis (CAA), CMP density checks, and foundry-required DFM rule checks — prioritize and resolve _c (critical) violations before tapeout.

Build and maintain robust PV automation infrastructure using Python, Perl, and Tcl — automate runset selection, job dispatch, result parsing, and signoff reporting.

Present PV status, waiver summaries, and signoff readiness reports to executive leadership and foundry partners at tapeout reviews.